CZ(4) BSD Programmer's Manual CZ(4)
cz - Cyclades-Z series multi-port serial adapter device driver
cz* at pci? dev ? function ?
The cz device driver supports the Cyclades-Z series of multi-port serial adapters. The Cyclades-Z is an intelligent serial controller comprising: • PLX9060ES PCI bus interface • Xilinx XC5204 FPGA • IDT R3052 MIPS CPU The MIPS CPU runs firmware provided by the device driver. Communication with the MIPS is performed by modifying data structures located in board local RAM or host RAM. The Cyclades-Z comes in three basic flavors: • Cyclades-8Zo rev. 1 -- This is an older 8-port board with no FPGA. The serial ports are provided by an octopus cable. • Cyclades-8Zo rev. 2 -- This is the newer 8-port board. The serial ports are provided by an octopus cable. • Cyclades-Ze -- This is the expandable version of the Cyclades- Z. It uses an HD-50 SCSI cable to connect the board to a 1U rack mountable serial expansion box. Each box has 16 RJ45 seri- al ports, and up to 4 boxes may be chained together, for a to- tal of 64 ports. Boxes 3 and 4 require their own external power supply, otherwise the firmware will refuse to start (as it can- not communicate with the UARTs in those boxes). The Cyclades-Z has several features to improve performance under high serial I/O load: • The board may operate in interrupt-driven mode or polled mode to reduce interrupt load. • Each channel has a large input and output buffer. • Each channel may be programmed to generate an interrupt based on reception of a specific character, e.g. a PPP End-Of-Frame character. • The MIPS CPU on the board performs all flow-control handling.
/dev/ttyZ?? dial-in (normal) TTY device /dev/cuaZ?? dial-out TTY device
intro(4), pci(4), termios(4), tty(4)
The cz driver first appeared in OpenBSD 3.0.
The cz driver was written by Jason R. Thorpe <firstname.lastname@example.org> and Bill Studenmund <email@example.com> of Zembu Labs, Inc.
The cz driver does not currently implement communication via host RAM. While this may improve performance by reducing the number of PCI memory space read/write cycles, it is not straightforward to implement with the current bus_dma(9) API. Interrupt mode has not been tested. There is no support for reading or writing the EEPROM connected to the PLX PCI bus controller. MirOS BSD #10-current May 17, 2000 1
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